In some synchronous transmission networks, stuffing is performed in order to absorb the frequency fluctuation of clock signal for operating various transmission apparatuses. Synchronous transmission networks that perform stuffing include, for example, SONET (Synchronous Optical Network)/SDH (Synchronous Digital Hierarchy), OTN (Optical Transport Network), etc.
Each transmission apparatus in a synchronous transmission network performs reception processing of a received frame received in synchronization with a reception clock extracted from the received frame, and then, converts the received data into data in synchronization with the internal clock of the apparatus.
FIG. 1 is a view depicting the construction of a clock conversion unit for converting received data received in synchronization with the reception clock into data in synchronization with an internal clock of the apparatus. The clock conversion unit 100 comprises clock dividers 101, 105, 110, 116, a serial-parallel converter 102, a write controller 103, and an elastic store memory 104.
The clock conversion unit 100 also comprises a phase shifter 111, a selector 112, counters 113 and 114, a decoder 115, and a phase comparator 117. In the description that follows and in the appended drawings, a serial-parallel converter, an elastic store memory, and a selector may be denoted as “S/P”, “ES”, and “SEL”, respectively.
The clock divider 101 divides the first clock extracted from a received frame in a prescribed division ratio. The clock divider 101 outputs the divided clock of the first clock to S/P 102, the write controller 103, ES 104 and to the counters 113 and 114.
S/P 102 receives data included in the received frame as input data, and converts the data into parallel data of prescribed bit width. The parallel data are inputted into the write controller 103.
The write controller 103 selects valid data from the input data in accordance with instruction information indicating a range of valid data in the input data, and outputs the valid data to write data bus WDT of ES 104. While outputting valid data, the write controller 103 also outputs write enable signal WEN to ES 104. Divided clock is inputted as write clock WCLK from the clock divider 101 to ES 104.
The clock divider 105 divides a second clock generated by a voltage control oscillator 200. The clock divider 105 inputs the divided clock of the second clock as read clock RCLK to ES 104. Input data stored in ES 104 are read out in accordance with a read enable signal in the timing in synchronization with the second clock. As a result, data inputted into the clock conversion unit 100 are converted to data in synchronization with the second clock.
When stuffing occurs, an amount of valid data per frame varies, and therefore, amount of data stored in ES 104 varies. When stuffing occurs, the clock conversion unit 100 absorbs variation of the amount of data stored in ES 104 by advancing or retarding the phase of read clock RCLK.
Phase control of read clock RCLK is carried out by controlling the generated frequency of the voltage control oscillator 200 that generates the second clock, and thereby changing the phase of the second clock. The construction and operation of the circuit that controls the generated frequency of the voltage control oscillator 200 will be described below.
The clock divider 110 divides the first clock. The phase shifter 111 outputs ten different clock signals by imparting phase shift of 36°×i, respectively, to the divided clock of the first clock, where i is an integer 0 to 9. Thus, the phase shifter 111 outputs ten clock signals by imparting phase shift in 10 steps with step width of 36° to the divided clock of the first clock.
FIG. 2 is a time chart depicting the clock signal outputted from the phase shifter 111. The signals CLK1 to CLK9 represent the output clocks from the phase shifter 111 with phase shift of 36°×i (i is an integer of 0 to 9), respectively, imparted to the divided clock of the first clock.
Referring to FIG. 1, SEL 112 selects one of clock signals CLK1 to CLK9 in accordance with the selection instructing signal outputted from the decoder 115, and outputs it to the phase comparator 117. In description of the construction of FIG. 1, the clock signal selected by SEL 112 may be denoted as “the third clock”.
The counter 113 receives a positive stuffing signal and a negative stuffing signal notifying occurrence of a positive stuffing and a negative stuffing as input EN(−) and EN(+), respectively, and counts the number of occurrences of stuffing. The counter 113 decreases the count by one each time it receives input EN(−), and increases the count by one each time it receives input EN(+).
When the count exceeds an upper bound value, the counter 113 outputs a carry-out signal CO(+), and resets the count to 0. When the count falls short of a lower bound value, the counter 113 outputs a carry-out signal CO(−), and resets the count to 0.
The counter 114 receives the carry-out signals CO(+) and CO(−) as inputs EN(+) and EN(−), respectively, and counts the number of times of carry-out signal reception. When the counter 114 receives a carry-out signal CO(+), it increases the count by one, and when the counter 114 receives a carry-out signal CO(−), it decreases the count by one.
When the count is less than 0, the counter 114 changes the count to 9. When the count exceeds 9, the counter 114 changes the count to 0. The counter 114 outputs the count Q to the decoder 115.
The decoder 115 generates a selection instructing signal for SEL 112 in accordance with the count Q. For example, the decoder 115 generates a selection instructing signal indicating the count Q (Q=0 to 9). SEL 112 outputs a clock obtained by imparting a phase shift of 36°×Q to the divided clock of the first clock as the third clock to the phase comparator 117.
Thus, if the upper bound value and the lower bound value of the count of the counter 113 are “k” and “−k”, respectively, the phase of the third clock inputted to the phase comparator 117 is advanced by 36° each time the count exceeds “k”. The phase of the third clock inputted to the phase comparator 117 is retarded by 36° each time the count falls short of “−k”.
The phase comparator 117 compares phase difference between the third clock outputted from SEL 112 and the divided clock CLKR obtained by dividing the second clock by the clock divider 116. A low-pass filter 201 generates a voltage signal in accordance with the phase difference detected by the phase comparator 117, and outputs the voltage signal to the voltage control oscillator 200. In the description that follows, a low-pass filter may be denoted as “LPF”.
The voltage control oscillator 200 controls the frequency of the second clock so as to maintain a prescribed phase relation between the phase of the third clock and the phase of the divided clock CLKR. Thus, when SEL 112 advances the phase of the third clock, the voltage control oscillator increases the frequency of the second clock such that the phase of the divided clock CLKR can follow the phase of the third clock. On the other hand, when SEL 112 retards the phase of the third clock, the voltage control oscillator 200 decreases the frequency of the second clock such that the phase of the divided clock CLKR can follow the phase of the third clock.
Phase control of the second clock by the voltage control oscillator 200 will be described below. FIG. 3A to FIG. 3C are views illustrating the frequency control of the second clock in the clock conversion unit 100. FIG. 3A depicts a state in which the clock CLK1 as depicted in FIG. 2 has been selected by SEL 112 and synchronization of the CLK1 with the divided clock CLKR of the second clock has been established.
FIG. 3B depicts a state in which SEL 112 selects the clock CLK2, and as a result, the phase of the clock outputted from SEL 112 is advanced. Immediately after CLK″ is selected, synchronization of the divided clock CLKR of the second clock with CLK2 is temporarily broken.
FIG. 3C depicts a state in which certain time has elapsed after FIG. 3B and synchronization of the divided clock CLKR of the second clock with CLK2 has been established. The voltage control oscillator 200 increases the frequency of the second clock since synchronization was broken as in FIG. 3B until synchronization is established again by advancing the phase of the divided clock CLKR of the second clock.
Thus, when negative stuffing occurs and an amount of data stored in ES 104 increases, the phase of the third clock is advanced. As a result, the voltage control oscillator 200 performs frequency control for increasing the frequency of the second clock to thereby advance read-out clock RCLK of ES 104 and to decrease the amount of data stored in ES 104.
On the contrary, when positive stuffing occurs and amount of data stored in ES 104 decreases, the phase of the third clock is retarded. As a result, the voltage control oscillator 200 performs frequency control for decreasing the frequency of the second clock to thereby retard read-out clock RCLK of ES 104 and to increase the amount of data stored in ES 104.
SDH (Synchronous Digital Hierarchy) transmission apparatus has been proposed in which an internal reference frame timing generated in a main signal processing unit containing a plurality of interface units is distributed to each interface unit by a frame timing distribution unit. In the above SDH transmission apparatus, by suppressing variation of the shift of the frame top position of each main signal from each interface unit to a minimum, change of frame timing of main signal can be achieved with minimum memory capacity without using pointer processing technology. In this way, size of the apparatus can be reduced to minimum, even if number of processing channels is increased.
Related art is disclosed in International Publication Pamphlet No. WO2000/074283.